The invention relates to a semiconductor circuit and a control method thereof and more particularly to a semiconductor circuit and a control method thereof wherein the interval between refreshing operations of a DRAM is prolonged.
With the progress in the integration of semiconductors, it has become possible to integrate a processor, a memory, or other circuit onto one chip. Further, with the progress in the technology of processes enabling a logic circuit such as a processor and DRAM (Dynamic RAM) to be merged on one chip, it has become possible to implement DRAM on a memory.
Each memory cell of DRAM is small, and made of a capacitor. Their advantage over the implementing of SRAM (Static RAM) is that the chip area can be greatly reduced. On the other hand, they bring such a disadvantage in that the electric charge stored thereon as data discharges with the passage of time and, hence, the data is lost. Therefore, it is necessary to make an operation to keep data from being lost. The memory cells of DRAM in general are arranged in a matrix array. The data stored in the memory cells are read out all at once for each row, detected by a sense amplifier, and the values of the data read out are written into the memory cells from which the data were read out. Such a sequence of operations is called xe2x80x9crefreshxe2x80x9d.
During the refreshing operation, the DRAM does not accept any access to itself. In the normal mode which allows read/write from outside the DRAM, the refreshing operation is executed by a DRAM controller outside the DRAM, but in a sleeping mode such as when backed up by battery, the refreshing operation is performed by a refresh controller inside the DRAM LSI. In the sleeping mode, any read/write access from outside the DRAM is not accepted.
Here, some problems arise when the DRAM and logic circuit are merged on the same LSI.
Merged DRAM/logic LSIs, however, have some disadvantages such that the DRAM portion of merged DRAM/logic LSIs might suffer from shorter data retention time. Heat and noise dissipated by the logic portion on the same chip could be harmful to the data retention time of the one-tip DRAM. When the ambient temperature rises, for example, from 25xc2x0 C. to 70xc2x0 C., the leakage current of the charge stored on the memory cell of the DRAM is increased by 30 fold and, hence, it becomes necessary to carry out the refreshing operation 30 times more frequently (Ito, xe2x80x9cVLSI Memory Designxe2x80x9d, Baifukan). In a system using conventional DRAM, refreshing operations are made at short intervals assuming the worst operating environmental conditions. Therefore, under normal temperature conditions, refreshing operations are being made at a great frequency.
There is great variation of the data retention time among the memory cells of DRAM and few memory cells have short data retention times (Iwata et al. xe2x80x9cCircuit Techniques for Super Low Retention Current DRAMxe2x80x9d, Technical Report of Institute of Electronics, Information, and Communication Engineers, ICD 95-50). However, refreshing operations are being made at the same cycle time for all of the rows. This means that refreshing operations are being made at a greater frequency than is needed for many of the rows, often including no memory cells that have a small actual capacity in terms of data retention time.
Further, all of the rows are refreshed whether the data held in DRAM are necessary for the logic circuit or not. In reality, only necessary data need be held in memory and, hence, unnecessary data need not be refreshed.
Such excessive refreshing invites wasteful power consumption.
Under these circumstances, means for decreasing the frequency of refreshing operations are being investigated. As a technique to decrease power consumption in the data retention mode of a conventional DRAM, there is a method 1 in which self-refreshing is conducted at a refreshing cycle time corresponding to temperature (Japanese Patent Laid-Open No. 6-215561). Further, as a technique to decrease power consumption in the normal mode of a conventional DRAM, there is a method 2 in which a control for the power supply and the decision as to whether a refreshing operation should be carried out is executed according to a flag set up in each memory area (Japanese Patent Laid-Open No. 5-324140, U.S. Pat. No. 5,469,559).
However, in Method 1 above, since the refreshing cycle time in the normal mode is adjusted to the memory cell having the shortest data retention time in the DRAM, there still remains the unresolved problem of power consumption in the normal mode. Further, Method 2 does not cope with variations in the data retention time.
What is more important is that the merged DRAM/logic LSI has a connection at a wide memory band width to achieve highly improved processing performance of the logic portion. In such an LSI, there arises a problem of conflict between refresh and access to the DRAM made by the logic circuit, thereby prolonging the time required for DRAM access and, hence, the processing performance of the logic circuit is deteriorated. This is a serious problem, comparable with the problem of achieving reduction in power consumption.
The first object of the present invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the number of refreshing operations by refreshing only the rows storing necessary data, and thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the access time due to the confliction between refresh and access to the DRAM.
A second object of the invention is to determine the rows storing data thereon according to the degree of importance of the data to, thereby, ensure saving important data without excessively shortening the refresh cycle time.
A third object of the invention is to have refreshing operations carried out at suitable cycle time in conformity with the temperatures to thereby achieve both reduction in power consumption and prevention of deterioration in the processing performance of the logic circuit.
In order to achieve the first object, the invention, in a control method of a merged DRAM/logic LSI, is characterized by comprising the steps of disposing data, which are combined so that the number of the rows storing data thereon may be reduced, on each of the rows of the DRAM and refreshing each of the rows having data stored thereon.
Another method to achieve the first object, in a control method of a merged DRAM/logic LSI, is characterized by comprising the steps of disposing arbitrary data of which periods from being written in to being read out are overlapping or close to each other are disposed on the same row of the DRAM and refreshing the row only during the time period from the writing in of the data at the first to the reading out thereof at the end.
A method to achieve the first and the second objects, in a control method of a merged DRAM/logic LSI, comprises the steps of obtaining the memory capacity required by an application using DRAM and storing data in DRAM in order from a row having a longer data retention time, with reference made to a table storing previously obtained data retention time of each row of DRAM, and setting a refreshing cycle adapted to the row whose data retention time is the shortest of the rows storing data thereon.
In this method, data may be disposed, when it is stored in the DRAM, on specific rows in accordance with the importance of the data.
A method to achieve the third object, in each of the above methods, is characterized by comprising the step of detecting the temperature of the semiconductor circuit and setting the refreshing cycle time of the DRAM according on the temperature.
A semiconductor circuit to achieve the first object is characterized by comprising means for disposing data, which are combined so that the number of the rows storing the data thereon may be reduced, on each of the rows of the DRAM and means for refreshing each of the rows having the data stored thereon.
Another semiconductor circuit which has achieved the first object is characterized by comprising means for disposing arbitrary data of which periods from being written in to being read out are overlapping or close to each other on the same row of DRAM, and means for refreshing the row only during the time period from the writing in of the data to the reading out thereof at the end.
A semiconductor circuit which has achieved the first and the second objects is characterized by comprising means for obtaining the memory capacity required by an application using DRAM and storing data in the DRAM in an order starting from a row having longer data retention time, with reference made to a table storing the previously obtained data retention time of each row of DRAM, and means for setting a refreshing cycle time adapted to the row whose data retention time is the shortest of the rows storing data thereon.
In this semiconductor circuit, there may be provided means for disposing data, when it is stored in the DRAM, on specific rows in accordance with the degree of importance of the data.
A semiconductor circuit which has achieved the third object, in each of the above semiconductor circuits, is characterized by comprising means for detecting the temperature of the semiconductor circuit and setting the refreshing cycle of the DRAM according to the temperature.
According to this invention, the following meritorious effects can be obtained:
(1) Since only the rows storing necessary data are refreshed, the number of refreshing operations can be decreased and, hence, reduction in power consumption and prevention of deterioration in the processing performance of the logic circuit caused by contention between refresh and DRAM access can be attained.
(2) Since the rows on which data are written are determined according to the degree of importance of the stored data, the need for excessively shortening the refreshing cycle can be eliminated and, hence, reduction in power consumption and prevention of deterioration in the processing performance of the logic circuit caused by contention between refresh and DRAM access can be attained.
(3) Since the refreshing cycle is set according to temperature, the need for excessively shortening the refreshing cycle can be eliminated and, hence, reduction in power consumption and prevention of deterioration in the processing performance of the logic circuit caused by contention between refresh and DRAM access can be attained.